? 2004 california micro devices corp. all rights reserved. 09/21/04 430 n. mccarthy blvd., milpitas, ca 95035-5112 tel: 408.263.3214 fax: 408.263.7846 www.calmicro.com 1 PACDN009 5 channel esd protection array features ? five channels of esd protection ? 8 kv contact, 15 kv air esd protection per channel (iec 61000-4-2 standard) ? 15 kv of esd protection per channel (hbm) ? low loading capacitance (3pf typical) ? low leakage current is ideal for battery-powered devices ? available in miniature 8-lead msop package ? lead-free version available applications ? consumer electronic products ? cellular phones ?pdas ? notebook computers ? desktop pcs ? digital cameras and camcorders ? vga (video) port protection for desktop and portable pcs product description the PACDN009 is a diode array designed to provide 5 channels of esd protection for electronic components or sub-systems. each channel consists of a pair of diodes which steers an esd current pulse to either the positive (v p ) or negative (v n ) supply. the PACDN009 protects against esd pulses up to 15kv human body model (100 pf capacitor discharging through a 1.5k ? resistor), and 8kv contact discharge, per international standard iec 61000-4-2. this device is particularly we ll-suited for portable elec- tronics (e.g., cellular phones, pdas, notebook comput- ers) because of its small package footprint, high esd protection level, and low load ing capacitance. it is also suitable for protecting video output lines and i/o ports in computers and peripherals and is ideal for a wide range of consumer electronics products. the PACDN009 is supplied in an 8-lead msop pack- age and is available with optional lead-free finishing. electrical schematic typical application circuit PACDN009 i/o port buffers connector expansion handheld/pda esd protection 14568 7 3 0.22 f* * capacitor should be placed as close as possible to pin7 1234 87 6 5 v p v n n.c.
? 2004 california micro devices corp. all rights reserved. 2 430 n. mccarthy blvd., milpitas, ca 95035-5112 tel: 408.263.3214 fax: 408.263.7846 www.calmicro.com 09/21/04 PACDN009 ordering information note 1: parts are shipped in tape & reel form unless otherwise specified. pin descriptions pin name type description 1 ch 1 i/o esd channel 2 n.c. - no connect 3v n gnd negative voltage supply rail or ground reference rail 4 ch 2 i/o esd channel 5 ch 3 i/o esd channel 6 ch 4 i/o esd channel 7v p supply positive voltage supply rail 8 ch 5 i/o esd channel package / pinout diagrams PACDN009 1 2 3 4 8 7 6 5 ch 1 n.c. v n ch 2 ch 5 v p ch 4 ch 3 top view note: this drawing is not to scale. 8-lead msop package part numbering information leads package standard finish lead-free finish ordering part number 1 part marking ordering part number 1 part marking 8 msop PACDN009m d009 PACDN009mr 009r
? 2004 california micro devices corp. all rights reserved. 09/21/04 430 n. mccarthy blvd., milpitas, ca 95035-5112 tel: 408.263.3214 fax: 408.263.7846 www.calmicro.com 3 PACDN009 specifications note 1: only one diode conducting at a time. note 1: all parameters specified at t a =25c unless otherwise noted. v p = 5v, v n = 0v unless noted. note 2: these parameters guaranteed by design and characterization. note 3: from i/o pins to v p or v n only. v p bypassed to v n with a 0.22 f ceramic capacitor (see appl ication information for more details). note 4: human body model per mil-std-883, method 3015, c discharge = 100pf, r discharge = 1.5k ?, v p = 5.0v, v n grounded. note 5: standard iec 61000-4-2 with c discharge = 150pf, r discharge = 330 ? , v p = 5.0v, v n grounded. absolute maximum ratings parameter rating units supply voltage (v p - v n )6.0v diode forward dc current (note 1) 20 ma operating temperature range -40 to +85 c storage temperature range -65 to +150 c dc voltage at any channel input (v n - 0.5) to (v p + 0.5) v package power rating msop package 200 mw standard operat ing conditions parameter rating units operating temperature range -40 to +85 c operating supply voltage (v p - v n ) 0 to 5.5 v electrical operating characteristics (see note 1) symbol parameter conditions min typ max units i p supply current (v p -v n )=5.5v 10 a v f diode forward voltage i f = 20ma 0.65 0.95 v v esd esd protection peak discharge voltage at any channel input, in system a) human body model, mil-std-883, method 3015 b) contact discharge per iec 61000-4-2 c) air discharge per iec 61000-4-2 note 3 notes 2,4 note 5 note 5 15 8 15 kv kv kv v cl channel clamp voltage positive transients negative transients @15kv esd hbm v p + 13.0 v n - 13.0 v v i leak channel leakage current 0 .1 1.0 a c in channel input capacitance @ 1 mhz, v p =5v, v n =0v, v in =2.5v; note 2 applies 35 pf
? 2004 california micro devices corp. all rights reserved. 4 430 n. mccarthy blvd., milpitas, ca 95035-5112 tel: 408.263.3214 fax: 408.263.7846 www.calmicro.com 09/21/04 PACDN009 performance information input capacitance vs. input voltage 0 1 2 3 4 5 012345 v in c in (pf) typical variation of c in vs. v in (v p = 5v, v n = 0v, 0.1 f chip capacitor between v p and v n )
? 2004 california micro devices corp. all rights reserved. 09/21/04 430 n. mccarthy blvd., milpitas, ca 95035-5112 tel: 408.263.3214 fax: 408.263.7846 www.calmicro.com 5 PACDN009 application information design considerations in order to realize the maximum protection against esd pulses, care must be taken in the pcb layout to minimize parasitic series inductances on the supply/ ground rails as well as the signal trace segment between the signal input (typically a connector) and the esd protection device. refer to figure 1 , which illus- trates an example of a positive esd pulse striking an input channel. the parasitic series inductances back to the power supply are represented by l 1 and l 2 . the voltage v cl on the line being protected is: v cl = fwd voltage drop of d 1 + v supply + l 1 x d(i esd ) / dt + l 2 x d(i esd ) / dt where i esd is the esd current pulse, and v supply is the positive supply voltage. an esd current pulse can ri se from zero to its peak value in a very short time. as an example, a level 4 contact discharge per the iec61000-4-2 standard results in a curren t pulse that rises from zero to 30 amps in 1ns. here d(i esd )/dt can be approximated by ? i esd / ? t, or 30/(1x10 -9 ). so just 10nh of series induc- tance (l 1 and l 2 combined) will lead to a 300v incre- ment in v cl ! similarly for negative esd pulses, parasitic series inductance from the v n pin to the ground rail will lead to drastically increased negative voltage on the line being protected. another consideration is the output impedance of the power supply for fast transient currents. most power supplies exhibit a much higher output impedance to fast transient current spikes. in the v cl equation above, the v supply term, in reality, is given by (v dc + i esd x r out ), where v dc and r out are the nominal supply dc output voltage and effective output imped- ance of the power supply respectively. for example, with r out equal to 1 ohm, we would see a 10v incre- ment in v cl for a peak i esd of 10a. if the inductances and resistance described above are close to zero, the rail-clam p esd protection diodes will do a good job of protection. however, since this is not possible in practical situations, a bypass capacitor must be used to absorb the very high frequency esd energy. so for any brand of rail-clamp esd protection diodes, a bypass capacitor should be connected between the v p pin of the diodes and the ground plane (v n pin of the diodes) as shown in the application cir- cuit diagram below. a value of 0.22f is adequate for iec-61000-4-2 level 4 contact discharge protection ( 8kv). ceramic chip capacitors mounted with short printed circuit board traces are good choices for this application. electrolytic capacitors should be avoided as they have poor high frequency characteristics. for extra protection, connect a zener diode in parallel with the bypass capacitor to mitigate the effects of the para- sitic series inductance inherent in the capacitor. the breakdown voltage of the zener diode should be slightly higher than the maximum supply voltage. as a general rule, the esd protection array should be located as close as possible to the point of entry of expected electrostatic discharges. the power supply bypass capacitor mentioned above should be as close to the v p pin of the protection array as possible, with minimum pcb trace lengths to the power supply, ground planes and between the signal input and the esd device to minimize st ray series inductance. additional information see also california micro devices application notes ap209, ?design consideratio ns for esd protection? and ap219, "esd pr otection for usb 2.0 systems"? figure 1. application of positive es d pulse between input channel and ground n l 2 l 1 v p v path of esd current pulse i one channel of pac dn009 channel input ground rail chassis ground positive supply rail system or circuitry being protected line being protected esd d 1 2 d 0a 20a v cl
? 2004 california micro devices corp. all rights reserved. 6 430 n. mccarthy blvd., milpitas, ca 95035-5112 tel: 408.263.3214 fax: 408.263.7846 www.calmicro.com 09/21/04 PACDN009 application information (cont?d) implementation examples esd events are very high-speed pulses with rise times in the range of 1ns or less. to effectively use the PACDN009, the following desi gn guidelines must be observed (as discussed in the application section): 1) the inductance from the v n and v p connections of the PACDN009 to ground must be very low. this includes the path through the v p decoupling capacitor to ground and the path to the power supply (as dis- cussed above). 2) the inductance between the connector pin to be protected and the PACDN009 channel input pin must be kept to a minimum. if there is a large inductance here, the esd event will find a lower impedance path which will more likely be th rough the devic e to be pro- tected. figure 2 shows the implementation schematic and figure 3 shows a possible layout for the PACDN009. in figure 3, notice the large vcc and ground areas with multiple via connections to the underlying reference planes and the positioning of the bypass capacitor. note how the signal lines to be pro- tected flow from the connector to the PACDN009 and then out to the device to be protected ( figure 3 ). this daisy chaining provides a low impedance path from the connector to the PACDN009 and a higher impedance path from the PACDN009 to the protected device. figure 2. typical esd protection implementation one channel of pac dn009 ground rail positive supply rail system or circuitry being protected d 1 2 d power supply optional zener diode for extra protection channel input decoupling capcitor 0.22 f line being protected
? 2004 california micro devices corp. all rights reserved. 09/21/04 430 n. mccarthy blvd., milpitas, ca 95035-5112 tel: 408.263.3214 fax: 408.263.7846 www.calmicro.com 7 PACDN009 application information (cont?d) figure 3. pcb layout recomendation
? 2004 california micro devices corp. all rights reserved. 8 430 n. mccarthy blvd., milpitas, ca 95035-5112 tel: 408.263.3214 fax: 408.263.7846 www.calmicro.com 09/21/04 PACDN009 mechanical details msop mechanical specifications the PACDN009 is supplied in an 8-lead msop pack- age. dimensions are presented below. for complete information on the msop-8 package, see the specific california micro devices package information document. * this is an approximate number which may vary. package dimensions for msop-8 package dimensions package msop leads 8 dimensions millimeters inches min max min max a 0.87 1.17 0.034 0.046 a1 0.05 0.25 0.002 0.010 b 0.30 (typ) 0.012 (typ) c 0.18 0.007 d 2.90 3.10 0.114 0.122 e 2.90 3.10 0.114 0.122 e 0.65 bsc 0.025 bsc h 4.78 4.98 0.188 0.196 l 0.52 0.54 0.017 0.025 # per tube 80 pieces* # per tape and reel 4000 pieces controlling dimension: inches mechanical package diagrams e d h 1234 8765 l end view c e b a a1 seating plane side view top view pin 1 marking
|
